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C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.17. E0CSR: USB0 Endpoint0 Control
Bit
Name
Type
Reset
7
SSUEND
R/W
0
6
SOPRDY
R/W
0
5
SDSTL
R/W
0
4
SUEND
R
0
3
DATAEND
R/W
0
2
STSTL
R/W
0
1
INPRDY
R/W
0
0
OPRDY
R
0
USB Register Address = 0x11
Bit Name Description
Write
Read
7
SSUEND Serviced Setup End
Bit.
Software should set this bit to 1
after servicing a Setup End (bit
This bit always reads 0.
SUEND) event. Hardware clears
the SUEND bit when software
writes 1 to SSUEND.
6
SOPRDY Serviced OPRDY Bit. Software should write 1 to this bit
after servicing a received End-
point0 packet. The OPRDY bit will
be cleared by a write of 1 to
SOPRDY.
This bit always reads 0.
5
4
SDSTL
SUEND
Send Stall Bit.
Software can write 1 to this bit to terminate the current transfer (due to an error condi-
tion, unexpected transfer request, etc.). Hardware will clear this bit to 0 when the STALL
handshake is transmitted.
Setup End Bit.
Hardware sets this read-only bit to 1 when a control transaction ends before software
has written 1 to the DATAEND bit. Hardware clears this bit when software writes 1 to
SSUEND.
3
DATAEND Data End Bit.
Software should write 1 to this bit: 1) When writing 1 to INPRDY for the last outgoing
data packet. 2) When writing 1 to INPRDY for a zero-length data packet. 3) When writ-
ing 1 to SOPRDY after servicing the last incoming data packet.
This bit is automatically cleared by hardware.
2
1
0
STSTL
INPRDY
OPRDY
Sent Stall Bit.
Hardware sets this bit to 1 after transmitting a STALL handshake signal. This flag must
be cleared by software.
IN Packet Ready Bit.
Software should write 1 to this bit after loading a data packet into the Endpoint0 FIFO
for transmit. Hardware clears this bit and generates an interrupt under either of the fol-
lowing conditions: 1) The packet is transmitted. 2) The packet is overwritten by an
incoming SETUP packet. 3) The packet is overwritten by an incoming OUT packet.
OUT Packet Ready Bit.
Hardware sets this read-only bit and generates an interrupt when a data packet has
been received. This bit is cleared only when software writes 1 to the SOPRDY bit.
Rev. 1.4
195
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